IMPORTANT VLSI QUESTIONS

AUTHOR : ARUN KATHIRU

1 : Why should you use a synchroniser when signals from outside world(means asynchronous to your design clock)are taken to your system?
2 : Fmax calculation of a sequential circuit?
3 : what is Tsetup(slack),Thold(slack)?
4 : What is built in self test?
5 : What is static timing analysis?
6 : Basic model of a test bench?
7 : How will you debug inside FPGA?
8 : Functional simulation of a particular design how did u do?
9 : ModelSim expertise?
10 : Timing paths in a design?
11 : Timing simulation experience?
12 : Timing parameters?
13 : PROJECTS explanation?
14 : SYnthesis Questions?
like, case statement synthesis? : MUX
if statement without else synthesis latch ..stuffs like that
14 : Digital ckt Questions
1)4:1 MUx from 2:1 MUX
2)8:1 Mux from 2:1 Mux
3)DECODER design
4)DEMUX design ,MUx design
5)AND,NOT* gates using 2:1 mux..
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