A place where u can find a lot of links to free books, share our knowledge in various technologies.software ,hardware, u name it
Friday, September 2, 2011
MY GOD
for the last i and a half months i am going through a lot of boredom...dont know things arent getting fine ....both getting a job in a cool country far from home and pickup...i have to pull things together..hopefully it comes fine for me.
Friday, June 24, 2011
some times attraction principles can backfire..
Even when i am a bachelor of attraction..some times..or most of the times i get trapped inside the attraction created subconsciously by others...i know it has to be avoided..
"---we should value those attraction which can return something to us for the entertainment we have given for the attraction...otherwise we have to move to another attraction...bluntly entertaining and pursuing attraction is an addiction..i know this and i am capable of meeting new attractions so i can leave my present attraction----"
principle of a jerk...
and i know that this holds true n every walks of life..i have to grow self-centric..before i start thnking of others..no wonders the attractions were behind kings and heroes..and they were so self centric....
"---we should value those attraction which can return something to us for the entertainment we have given for the attraction...otherwise we have to move to another attraction...bluntly entertaining and pursuing attraction is an addiction..i know this and i am capable of meeting new attractions so i can leave my present attraction----"
principle of a jerk...
and i know that this holds true n every walks of life..i have to grow self-centric..before i start thnking of others..no wonders the attractions were behind kings and heroes..and they were so self centric....
Tuesday, June 7, 2011
Something about death
....I have thought many times how we are going to die...What will be our final thoughts before we pass away...even though i understand it doesnt matter.I don wanna die that regular bed death or die as a patient.When i die i wanna die healthy with my body and mind in good shape..We are anyway born here why not live an exciting life..why not live the way like Mr Bond lived....I remember the sentence from TROY...."Let them say i lived in the time of hector ,the horse tamer....Let them say i lived in the time of Achillies"...I feel all these warriors knew the simple facts about life which is just propagating our genes to the next generation...since they knew this early they decided to make their lives more exciting..more thrilling...they were self centric..they lived a jerk life...they held on only their own values...coz they knew it wouldnt last long...i have taken a lot of decisions for myself and i am sure i will make all of them happen....when i die i will die the death of a king...i will have everything that i can possibly wish for....i will not let someone control me for i am capable of controlling myself..i will have made some books for the next generation.
Friday, May 6, 2011
Friday, March 11, 2011
PRETTY COOL...
I just came to know that..there are two guitarist,one violinist and one drummer in my office.I mean how cool is that.....?...Learning opportunities...
Wednesday, March 2, 2011
7 BIT CRC GENERATOR CIRCUIT
Hey guys today i am posting THE CRC7Bit generator Verilog code here.I have not checked it for compilation errors,but that you can solve very easily.if you understand the code it will be eazy for you to extend it to 16 bit CRC generator.Its generic in the sense all the connection vectors are programmable...all you need to give is the polynimial for connection vectors for each bit...i plan to explain it with a diagram later on..But for now only the Verilog code.....The Diagram will be coming soon....
/* GENERIC 7 bit CRC GENERATOR CKT
the module creates 7 bit CRC depending on the polynomial given to it as input and gives out serial 7 bit serial CRC. "enable" should be high for the input bits which need to be shifted into the 7 bit CRC generator.crc_Shift should be high to get the serial crc data out of this module.The same can be used for the CRC verification at the receiver end,for this reason
crc_7bits is ported out.
Designer: Arun Kathiru Date: March 2 2011 */
module CRC7(
clk,
serial_Data,
crc_7bits,
data_Out,
enable,
crc_Shift,
poly_0Bit, /*which bits should be xored and given to lsb should be given as polynomial*/
poly_1Bit, /*which bits should be xored and given to 1st bit should be given as polynomial*/
poly_2Bit, /*which bits should be xored and given to 2nd bit should be given as polynomial*/
poly_3Bit, /*which bits should be xored and given to 3rd bit lsb should be given as polynomial*/
poly_4bit, /*which bits should be xored and given to 4th bit lsb should be given as polynomial*/
poly_5bit, /*which bits should be xored and given to 5th bit lsb should be given as polynomial*/
poly_6bit /*which bits should be xored and given to 6th bit lsb should be given as polynomial*/
);
input clk,
input serial_Data;
input crc_Shift;
input enable;
input [7:0] poly_0Bit; /* the seventh bit should be 0 if u dont want to xor the serial_Data with other bits,otherwise its 1*/
input [7:0] poly_1Bit;
input [7:0] poly_2Bit;
input [7:0] poly_3Bit;
input [7:0] poly_4Bit;
input [7:0] poly_5Bit;
input [7:0] poly_6Bit;
output reg [6:0] crc_7bits;
reg [6:0] poly_0Bit;
reg [6:0] poly_1Bit;
reg [6:0] poly_2Bit;
reg [6:0] poly_3Bit;
reg [6:0] poly_4Bit;
reg [6:0] poly_5Bit;
reg [6:0] poly_6Bit;
wire crc_0Bit;
wire crc_1Bit;
wire crc_2Bit;
wire crc_3Bit;
wire crc_4Bit;
wire crc_5Bit;
wire crc_6Bit;
output data_Out;
assign crc_0Bit = (poly_0Bit(6) AND crc_7bits(6)) XOR (poly_0Bit(5) AND crc_7bits(5)) XOR (poly_0Bit(4) AND crc_7bits(4))
XOR(poly_0Bit(3) AND crc_7bits(3)) XOR (poly_0Bit(2) AND crc_7bits(2)) XOR (poly_0Bit(1) AND crc_7bits(1)) XOR(poly_0Bit(0) AND crc_7bits(0)) XOR (poly_0Bit(7) AND serial_Data);
assign crc_1Bit = (poly_1Bit(6) AND crc_7bits(6)) XOR (poly_1Bit(5) AND crc_7bits(5)) XOR (poly_1Bit(4) AND crc_7bits(4))
XOR(poly_1Bit(3) AND crc_7bits(3)) XOR (poly_1Bit(2) AND crc_7bits(2)) XOR (poly_1Bit(1) AND crc_7bits(1)) XOR(poly_1Bit(0) AND crc_7bits(0)) XOR (poly_1Bit(7) AND serial_Data);
assign crc_2Bit = (poly_2Bit(6) AND crc_7bits(6)) XOR (poly_2Bit(5) AND crc_7bits(5)) XOR (poly_2Bit(4) AND crc_7bits(4))
XOR(poly_2Bit(3) AND crc_7bits(3)) XOR (poly_2Bit(2) AND crc_7bits(2)) XOR (poly_2Bit(1) AND crc_7bits(1)) XOR(poly_2Bit(0) AND crc_7bits(0))XOR (poly_2Bit(7) AND serial_Data);
assign crc_3Bit =(poly_3Bit(6) AND crc_7bits(6)) XOR (poly_3Bit(5) AND crc_7bits(5)) XOR (poly_3Bit(4) AND crc_7bits(4))
XOR(poly_3Bit(3) AND crc_7bits(3)) XOR (poly_3Bit(2) AND crc_7bits(2)) XOR (poly_3Bit(1) AND crc_7bits(1)) XOR(poly_3Bit(0) AND crc_7bits(0))XOR (poly_3Bit(7) AND serial_Data);
assign crc_4Bit =(poly_4Bit(6) AND crc_4bits(6)) XOR (poly_4Bit(5) AND crc_7bits(5)) XOR (poly_4Bit(4) AND crc_7bits(4))
XOR(poly_4Bit(3) AND crc_7bits(3)) XOR (poly_4Bit(2) AND crc_7bits(2)) XOR (poly_4Bit(1) AND crc_7bits(1)) XOR(poly_4Bit(0) AND crc_7bits(0))XOR (poly_4Bit(7) AND serial_Data);
assign crc_5Bit =(poly_5Bit(6) AND crc_7bits(6)) XOR (poly_5Bit(5) AND crc_7bits(5)) XOR (poly_5Bit(4) AND crc_7bits(4))
XOR(poly_5Bit(3) AND crc_7bits(3)) XOR (poly_5Bit(2) AND crc_7bits(2)) XOR (poly_5Bit(1) AND crc_7bits(1)) XOR(poly_5Bit(0) AND crc_7bits(0))XOR (poly_5Bit(7) AND serial_Data);
assign crc_6Bit = (poly_6Bit(6) AND crc_7bits(6)) XOR (poly_6Bit(5) AND crc_7bits(5)) XOR (poly_6Bit(4) AND crc_7bits(4))
XOR(poly_6Bit(3) AND crc_7bits(3)) XOR (poly_6Bit(2) AND crc_7bits(2)) XOR (poly_6Bit(1) AND crc_7bits(1)) XOR(poly_6Bit(0) AND crc_7bits(0))XOR (poly_6Bit(7) AND serial_Data);
assign data_Out = crc_7bits[6];
always@(posedge clk,negedge reset_n)
begin
if(!reset_n)
crc_7bits <= 7'b0;
else
begin
if(enable == 1'b1)
begin
crc_7bits[6:0] <= {crc_6Bit,crc_5Bit,crc_4Bit,crc_3Bit,crc_2Bit,crc_1Bit,crc_0Bit};
end
else if (crc_Shift == 1'b1)
crc_7bits[6:0] <= {crc_7bits[5:0],1'b0};
end
end
endmodule
/* GENERIC 7 bit CRC GENERATOR CKT
the module creates 7 bit CRC depending on the polynomial given to it as input and gives out serial 7 bit serial CRC. "enable" should be high for the input bits which need to be shifted into the 7 bit CRC generator.crc_Shift should be high to get the serial crc data out of this module.The same can be used for the CRC verification at the receiver end,for this reason
crc_7bits is ported out.
Designer: Arun Kathiru Date: March 2 2011 */
module CRC7(
clk,
serial_Data,
crc_7bits,
data_Out,
enable,
crc_Shift,
poly_0Bit, /*which bits should be xored and given to lsb should be given as polynomial*/
poly_1Bit, /*which bits should be xored and given to 1st bit should be given as polynomial*/
poly_2Bit, /*which bits should be xored and given to 2nd bit should be given as polynomial*/
poly_3Bit, /*which bits should be xored and given to 3rd bit lsb should be given as polynomial*/
poly_4bit, /*which bits should be xored and given to 4th bit lsb should be given as polynomial*/
poly_5bit, /*which bits should be xored and given to 5th bit lsb should be given as polynomial*/
poly_6bit /*which bits should be xored and given to 6th bit lsb should be given as polynomial*/
);
input clk,
input serial_Data;
input crc_Shift;
input enable;
input [7:0] poly_0Bit; /* the seventh bit should be 0 if u dont want to xor the serial_Data with other bits,otherwise its 1*/
input [7:0] poly_1Bit;
input [7:0] poly_2Bit;
input [7:0] poly_3Bit;
input [7:0] poly_4Bit;
input [7:0] poly_5Bit;
input [7:0] poly_6Bit;
output reg [6:0] crc_7bits;
reg [6:0] poly_0Bit;
reg [6:0] poly_1Bit;
reg [6:0] poly_2Bit;
reg [6:0] poly_3Bit;
reg [6:0] poly_4Bit;
reg [6:0] poly_5Bit;
reg [6:0] poly_6Bit;
wire crc_0Bit;
wire crc_1Bit;
wire crc_2Bit;
wire crc_3Bit;
wire crc_4Bit;
wire crc_5Bit;
wire crc_6Bit;
output data_Out;
assign crc_0Bit = (poly_0Bit(6) AND crc_7bits(6)) XOR (poly_0Bit(5) AND crc_7bits(5)) XOR (poly_0Bit(4) AND crc_7bits(4))
XOR(poly_0Bit(3) AND crc_7bits(3)) XOR (poly_0Bit(2) AND crc_7bits(2)) XOR (poly_0Bit(1) AND crc_7bits(1)) XOR(poly_0Bit(0) AND crc_7bits(0)) XOR (poly_0Bit(7) AND serial_Data);
assign crc_1Bit = (poly_1Bit(6) AND crc_7bits(6)) XOR (poly_1Bit(5) AND crc_7bits(5)) XOR (poly_1Bit(4) AND crc_7bits(4))
XOR(poly_1Bit(3) AND crc_7bits(3)) XOR (poly_1Bit(2) AND crc_7bits(2)) XOR (poly_1Bit(1) AND crc_7bits(1)) XOR(poly_1Bit(0) AND crc_7bits(0)) XOR (poly_1Bit(7) AND serial_Data);
assign crc_2Bit = (poly_2Bit(6) AND crc_7bits(6)) XOR (poly_2Bit(5) AND crc_7bits(5)) XOR (poly_2Bit(4) AND crc_7bits(4))
XOR(poly_2Bit(3) AND crc_7bits(3)) XOR (poly_2Bit(2) AND crc_7bits(2)) XOR (poly_2Bit(1) AND crc_7bits(1)) XOR(poly_2Bit(0) AND crc_7bits(0))XOR (poly_2Bit(7) AND serial_Data);
assign crc_3Bit =(poly_3Bit(6) AND crc_7bits(6)) XOR (poly_3Bit(5) AND crc_7bits(5)) XOR (poly_3Bit(4) AND crc_7bits(4))
XOR(poly_3Bit(3) AND crc_7bits(3)) XOR (poly_3Bit(2) AND crc_7bits(2)) XOR (poly_3Bit(1) AND crc_7bits(1)) XOR(poly_3Bit(0) AND crc_7bits(0))XOR (poly_3Bit(7) AND serial_Data);
assign crc_4Bit =(poly_4Bit(6) AND crc_4bits(6)) XOR (poly_4Bit(5) AND crc_7bits(5)) XOR (poly_4Bit(4) AND crc_7bits(4))
XOR(poly_4Bit(3) AND crc_7bits(3)) XOR (poly_4Bit(2) AND crc_7bits(2)) XOR (poly_4Bit(1) AND crc_7bits(1)) XOR(poly_4Bit(0) AND crc_7bits(0))XOR (poly_4Bit(7) AND serial_Data);
assign crc_5Bit =(poly_5Bit(6) AND crc_7bits(6)) XOR (poly_5Bit(5) AND crc_7bits(5)) XOR (poly_5Bit(4) AND crc_7bits(4))
XOR(poly_5Bit(3) AND crc_7bits(3)) XOR (poly_5Bit(2) AND crc_7bits(2)) XOR (poly_5Bit(1) AND crc_7bits(1)) XOR(poly_5Bit(0) AND crc_7bits(0))XOR (poly_5Bit(7) AND serial_Data);
assign crc_6Bit = (poly_6Bit(6) AND crc_7bits(6)) XOR (poly_6Bit(5) AND crc_7bits(5)) XOR (poly_6Bit(4) AND crc_7bits(4))
XOR(poly_6Bit(3) AND crc_7bits(3)) XOR (poly_6Bit(2) AND crc_7bits(2)) XOR (poly_6Bit(1) AND crc_7bits(1)) XOR(poly_6Bit(0) AND crc_7bits(0))XOR (poly_6Bit(7) AND serial_Data);
assign data_Out = crc_7bits[6];
always@(posedge clk,negedge reset_n)
begin
if(!reset_n)
crc_7bits <= 7'b0;
else
begin
if(enable == 1'b1)
begin
crc_7bits[6:0] <= {crc_6Bit,crc_5Bit,crc_4Bit,crc_3Bit,crc_2Bit,crc_1Bit,crc_0Bit};
end
else if (crc_Shift == 1'b1)
crc_7bits[6:0] <= {crc_7bits[5:0],1'b0};
end
end
endmodule
Subscribe to:
Posts (Atom)